1. Field of the Invention:
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a shallow trench isolation (STI) structure in a semiconductor substrate.
2. Description of Related Art:
The purpose of an isolation structure in an IC device is to prevent carriers, such as electrons or electron holes, from drifting between two adjacent device elements through a semiconductor substrate to cause a current leakage. For example, carriers drift between two adjacent transistors through their substrate. Conventionally, isolation structures are formed between field effect transistors (FETs) in an IC device, such as a dynamic random access memory (DRAM) device, to prevent a current leakage from occurring. The isolation structures usually are formed directly on the semiconductor substrate. For example, a local oxidation (LOCOS) process is a typical isolation process widely used to form a field oxide (FOX) structure for isolating a metal oxide semiconductor (MOS) transistor. LOCOS technology has been well developed so that it can effectively isolate the MOS transistor with a good reliability of performance and low fabrication cost. However, LOCOS technology still has some problems. One example is an occurrence of a bird's beak on the edge of the FOX structure. The bird's beak reduces the isolation performance when device dimension is reduced. Hence, LOCOS technology is not suitable for a lightly integrated device.
Shallow trench isolation (STI) is another widely used technology for isolating device elements. The 511 structure is particularly suitable for a highly reduced dimension. The STI process usually uses a silicon nitride layer as a mask to form a trench in the substrate by anisotropic etching. Then the trench is filled with an oxide material serving as an isolating structure, which has a top surface as high as the substrate surface. This STI structure allows it to be fabricated with a greatly reduced dimension. Generally, as a device element dimension, such as a transistor dimensions is reduced, the isolation structure dimension is necessary to be accordingly reduced. The STI structure is a good candidates.
However, a conventional STI structure needs a chemical mechanical polish (CMP) process to planarize the oxide matter filled in the trench in order to obtain a planar surface for subsequent fabrication processes. A planarity of a planalized surface depends on many factors such as rotation speed of a polishing pad, slurry supplying rate, global temperature, PH quantity, grind particle size distribution, temperature at the polishing pad, and polishing pad material. If all those factors are not properly optimized during CMP process, different polishing rates may occur at different locations. For instances, a polishing rate at the inner portion of the wafer is larger than that at the outer portion of the wafer. This cause a poor uniformity of the wafer surface. Moreover, a recess also often occurs at the STI structure since it usually includes silicon oxide, which is softer than a mask layer made of silicon nitride. Each device element is isolated by STI structures. Since the device element density at the wafer is not away the same, the wafer usually includes several dense pattern regions and a loose pattern region between two dense pattern regions. Usually, there is only a wider STI structure at the loose patter region to separate the dense pattern regions. The recess effect on the wider STI structure at the loose pattern region is more severe than that at the dense pattern region.
A severe recess effect occurring at the wider STI structure may cause a charge accumulation on each upper corner of the wider STI structure, and further inducing a subthreshold current to shift a device normal threshold voltage. This phenomenon is usually called a kink effect. Moreover, the CMP process also causes a non-uniformity substrate surface.